Sunday, 15 April 2012
Sunday, 8 April 2012
Sunday, 25 March 2012
Week 8
1) Modify the programming to display output text at LCD using verilog HDL using 2 switch selector to display output AINI and KIERA.
else if (data_in == 1) => for switch 2
Figure 1: LCD Specification
Coding for 2 SWITCH
endmodule
Figure 2: Pin assignments for the toggle switches.
Table 1: Pin assignments for LCD coding
Figure 3: Show the coding have no error successful
Figure 4: Show the coding successful
Figure 5: RTL View
OUTPUT
Switch 1 for display AINI
Figure 6 : Output LCD display AINI
Switch 2 for display KIERA
Figure 7 : Output LCD display KIERA
- The coding must add
else if (data_in == 1) => for switch 2
Coding for 2 SWITCH
Module LCD_TEST (
// Host Side
input
iCLK,iRST_N,
input data_in,
// LCD Side
output [7:0] LCD_DATA,
output
LCD_RW,LCD_EN,LCD_RS,
output reg
LCD_ON,LCD_BLON
);
// Internal
Wires/Registers
reg [5:0] LUT_INDEX;
reg [8:0] LUT_DATA;
reg [5:0] mLCD_ST;
reg [17:0] mDLY;
reg mLCD_Start;
reg [7:0] mLCD_DATA;
reg mLCD_RS;
wire mLCD_Done;
parameter LCD_INTIAL = 0;
parameter LCD_LINE1 = 5;
parameter LCD_CH_LINE = LCD_LINE1+16;
parameter LCD_LINE2 = LCD_LINE1+16+1;
parameter LUT_SIZE = LCD_LINE1+32+1;
initial
begin
LCD_ON=1;
LCD_BLON=1;
end
always@(posedge iCLK or negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mLCD_ST <= 0;
mDLY <= 0;
mLCD_Start <= 0;
mLCD_DATA <= 0;
mLCD_RS <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mLCD_ST)
0: begin
mLCD_DATA <= LUT_DATA[7:0];
mLCD_RS <= LUT_DATA[8];
mLCD_Start <= 1;
mLCD_ST <= 1;
end
1: begin
if(mLCD_Done)
begin
mLCD_Start <= 0;
mLCD_ST <= 2;
end
end
2: begin
if(mDLY<18'h3FFFE)
mDLY <= mDLY
+ 1'b1;
else
begin
mDLY <= 0;
mLCD_ST <= 3;
end
end
3: begin
LUT_INDEX <= LUT_INDEX
+ 1'b1;
mLCD_ST <= 0;
end
endcase
end
end
end
always
if (data_in == 0)
begin
case(LUT_INDEX)
// Initial
LCD_INTIAL+0: LUT_DATA <= 9'h038;
LCD_INTIAL+1: LUT_DATA <= 9'h00C;
LCD_INTIAL+2: LUT_DATA <= 9'h001;
LCD_INTIAL+3: LUT_DATA <= 9'h006;
LCD_INTIAL+4: LUT_DATA <= 9'h080;
// Line 1
LCD_LINE1+0: LUT_DATA <= 9'h141; // <Altera
DE2 Kit>
LCD_LINE1+1: LUT_DATA <= 9'h149;
LCD_LINE1+2: LUT_DATA <= 9'h14E;
LCD_LINE1+3: LUT_DATA <= 9'h149;
/*LCD_LINE1+4: LUT_DATA <= 9'h149;
LCD_LINE1+5: LUT_DATA <= 9'h14E;
LCD_LINE1+6: LUT_DATA <= 9'h147;
/*LCD_LINE1+7: LUT_DATA <= 9'h144;
LCD_LINE1+8: LUT_DATA <= 9'h145;
LCD_LINE1+9: LUT_DATA <= 9'h132;
LCD_LINE1+10: LUT_DATA <= 9'h120;
LCD_LINE1+11: LUT_DATA <= 9'h142;
LCD_LINE1+12: LUT_DATA <= 9'h16F;
LCD_LINE1+13: LUT_DATA <= 9'h161;
LCD_LINE1+14: LUT_DATA <= 9'h172;
LCD_LINE1+15: LUT_DATA <= 9'h164;*/
// Change Line
LCD_CH_LINE: LUT_DATA <= 9'h0C0;
// Line 2
/*LCD_LINE2+0: LUT_DATA <= 9'h14E; // Nice To See You!
LCD_LINE2+1: LUT_DATA <= 9'h169;
LCD_LINE2+2: LUT_DATA <= 9'h163;
LCD_LINE2+3: LUT_DATA <= 9'h165;
LCD_LINE2+4: LUT_DATA <= 9'h120;
LCD_LINE2+5: LUT_DATA <= 9'h154;
LCD_LINE2+6: LUT_DATA <= 9'h16F;
LCD_LINE2+7: LUT_DATA <= 9'h120;
LCD_LINE2+8: LUT_DATA <= 9'h153;
LCD_LINE2+9: LUT_DATA <= 9'h165;
LCD_LINE2+10: LUT_DATA <= 9'h165;
LCD_LINE2+11: LUT_DATA <= 9'h120;
LCD_LINE2+12: LUT_DATA <= 9'h159;
LCD_LINE2+13: LUT_DATA <= 9'h16F;
LCD_LINE2+14: LUT_DATA <= 9'h175;
LCD_LINE2+15: LUT_DATA <= 9'h121;*/
default: LUT_DATA <= 9'dx
;
endcase
end
else if (data_in == 1)
begin
case(LUT_INDEX)
// Initial
LCD_INTIAL+0: LUT_DATA <= 9'h038;
LCD_INTIAL+1: LUT_DATA <= 9'h00C;
LCD_INTIAL+2: LUT_DATA <= 9'h001;
LCD_INTIAL+3: LUT_DATA <= 9'h006;
LCD_INTIAL+4: LUT_DATA <= 9'h080;
// Line 1
LCD_LINE1+0: LUT_DATA <= 9'h14B; // <Altera
DE2 Kit>
LCD_LINE1+1: LUT_DATA <= 9'h149;
LCD_LINE1+2: LUT_DATA <= 9'h145;
LCD_LINE1+3: LUT_DATA <= 9'h152;
LCD_LINE1+4: LUT_DATA <= 9'h141;
/*LCD_LINE1+5: LUT_DATA <= 9'h14E;
LCD_LINE1+6: LUT_DATA <= 9'h147;
/*LCD_LINE1+7: LUT_DATA <= 9'h144;
LCD_LINE1+8: LUT_DATA <= 9'h145;
LCD_LINE1+9: LUT_DATA <= 9'h132;
LCD_LINE1+10: LUT_DATA <= 9'h120;
LCD_LINE1+11: LUT_DATA <= 9'h142;
LCD_LINE1+12: LUT_DATA <= 9'h16F;
LCD_LINE1+13: LUT_DATA <= 9'h161;
LCD_LINE1+14: LUT_DATA <= 9'h172;
LCD_LINE1+15: LUT_DATA <= 9'h164;*/
// Change Line
LCD_CH_LINE: LUT_DATA <= 9'h0C0;
// Line 2
/*LCD_LINE2+0: LUT_DATA <= 9'h14E; // Nice To See You!
LCD_LINE2+1: LUT_DATA <= 9'h169;
LCD_LINE2+2: LUT_DATA <= 9'h163;
LCD_LINE2+3: LUT_DATA <= 9'h165;
LCD_LINE2+4: LUT_DATA <= 9'h120;
LCD_LINE2+5: LUT_DATA <= 9'h154;
LCD_LINE2+6: LUT_DATA <= 9'h16F;
LCD_LINE2+7: LUT_DATA <= 9'h120;
LCD_LINE2+8: LUT_DATA <= 9'h153;
LCD_LINE2+9: LUT_DATA <= 9'h165;
LCD_LINE2+10: LUT_DATA <= 9'h165;
LCD_LINE2+11: LUT_DATA <= 9'h120;
LCD_LINE2+12: LUT_DATA <= 9'h159;
LCD_LINE2+13: LUT_DATA <= 9'h16F;
LCD_LINE2+14: LUT_DATA <= 9'h175;
LCD_LINE2+15: LUT_DATA <= 9'h121;*/
default: LUT_DATA <= 9'dx
;
endcase
end
LCD_Controller u0(
// Host Side
.iDATA(mLCD_DATA),
.iRS(mLCD_RS),
.iStart(mLCD_Start),
.oDone(mLCD_Done),
.iCLK(iCLK),
.iRST_N(iRST_N),
// LCD Interface
.LCD_DATA(LCD_DATA),
.LCD_RW(LCD_RW),
.LCD_EN(LCD_EN),
.LCD_RS(LCD_RS)
);
Figure 2: Pin assignments for the toggle switches.
Table 1: Pin assignments for LCD coding
Figure 3: Show the coding have no error successful
Figure 5: RTL View
OUTPUT
Switch 1 for display AINI
Figure 6 : Output LCD display AINI
Switch 2 for display KIERA
Figure 7 : Output LCD display KIERA
Saturday, 17 March 2012
WEEK 7
1) Do the
programming to display output text at LCD using verilog HDL. From this
programming I use 1 switch selector to display output AINI.
- The LCD module has built-in fonts and can be used to display text by sending appropriate commands to the display controller, which is called HD44780. Detailed information for using the display is available in its datasheet, which can be found on the manufacturer's web site, and from the Datasheet folder on the DE2 System CD-ROM. A schematic diagram of the LCD module showing connections to the Cyclone II FPGA is given in Figure 1. The associated pin assignments appear in Table 1.
Figure 1: Schematic diagram of the LCD module.
Table 1: Pin assignments for the LCD module.
.png)
Figure 2: Timing characteristic (read operation)
.png)
Figure 3: Timing characteristic (write operation)
Figure 4: LCD Specification
Coding for 1 SWITCH
Module LCD_TEST (
// Host Side
input iCLK,iRST_N,
input data_in,
// LCD Side
output [7:0] LCD_DATA,
output LCD_RW,LCD_EN,LCD_RS,
output reg LCD_ON,LCD_BLON
);
//Internal Wires/Registers
reg [5:0] LUT_INDEX;
reg [8:0] LUT_DATA;
reg [5:0] mLCD_ST;
reg [17:0] mDLY;
reg mLCD_Start;
reg [7:0] mLCD_DATA;
reg mLCD_RS;
wire mLCD_Done;
parameter LCD_INTIAL = 0;
parameter LCD_LINE1 = 5;
parameter LCD_CH_LINE = LCD_LINE1+16;
parameter LCD_LINE2 = LCD_LINE1+16+1;
parameter LUT_SIZE = LCD_LINE1+32+1;
initial
begin
LCD_ON=1;
LCD_BLON=1;
end
always@(posedge iCLK or
negedge iRST_N)
begin
if(!iRST_N)
begin
LUT_INDEX <= 0;
mLCD_ST <= 0;
mDLY <= 0;
mLCD_Start <= 0;
mLCD_DATA <= 0;
mLCD_RS <= 0;
end
else
begin
if(LUT_INDEX<LUT_SIZE)
begin
case(mLCD_ST)
0: begin
mLCD_DATA <= LUT_DATA[7:0];
mLCD_RS <= LUT_DATA[8];
mLCD_Start <= 1;
mLCD_ST <= 1;
end
1: begin
if(mLCD_Done)
begin
mLCD_Start <= 0;
mLCD_ST <= 2;
end
end
2: begin
if(mDLY<18'h3FFFE)
mDLY <= mDLY
+ 1'b1;
else
begin
mDLY <= 0;
mLCD_ST <= 3;
end
end
3: begin
LUT_INDEX <= LUT_INDEX
+ 1'b1;
mLCD_ST <= 0;
end
endcase
end
end
end
always
begin
case(LUT_INDEX)
// Initial
LCD_INTIAL+0: LUT_DATA <= 9'h038;
LCD_INTIAL+1: LUT_DATA <= 9'h00C;
LCD_INTIAL+2: LUT_DATA <= 9'h001;
LCD_INTIAL+3: LUT_DATA <= 9'h006;
LCD_INTIAL+4: LUT_DATA <= 9'h080;
// Line 1
LCD_LINE1+0: LUT_DATA <= 9'h141; // <Altera DE2 Kit>
LCD_LINE1+1: LUT_DATA <= 9'h149;
LCD_LINE1+2: LUT_DATA <= 9'h14E;
LCD_LINE1+3: LUT_DATA <= 9'h149;
/*LCD_LINE1+4: LUT_DATA <= 9'h149;
LCD_LINE1+5: LUT_DATA <= 9'h14E;
LCD_LINE1+6: LUT_DATA <= 9'h147;
/*LCD_LINE1+7: LUT_DATA <= 9'h144;
LCD_LINE1+8: LUT_DATA <= 9'h145;
LCD_LINE1+9: LUT_DATA <= 9'h132;
LCD_LINE1+10: LUT_DATA <= 9'h120;
LCD_LINE1+11: LUT_DATA <= 9'h142;
LCD_LINE1+12: LUT_DATA <= 9'h16F;
LCD_LINE1+13: LUT_DATA <= 9'h161;
LCD_LINE1+14: LUT_DATA <= 9'h172;
LCD_LINE1+15: LUT_DATA <= 9'h164;*/
// Change Line
LCD_CH_LINE: LUT_DATA <= 9'h0C0;
// Line 2
/*LCD_LINE2+0: LUT_DATA <= 9'h14E;//Nice To See You!
LCD_LINE2+1: LUT_DATA <= 9'h169;
LCD_LINE2+2: LUT_DATA <= 9'h163;
LCD_LINE2+3: LUT_DATA <= 9'h165;
LCD_LINE2+4: LUT_DATA <= 9'h120;
LCD_LINE2+5: LUT_DATA <= 9'h154;
LCD_LINE2+6: LUT_DATA <= 9'h16F;
LCD_LINE2+7: LUT_DATA <= 9'h120;
LCD_LINE2+8: LUT_DATA <= 9'h153;
LCD_LINE2+9: LUT_DATA <= 9'h165;
LCD_LINE2+10: LUT_DATA <= 9'h165;
LCD_LINE2+11: LUT_DATA <= 9'h120;
LCD_LINE2+12: LUT_DATA <= 9'h159;
LCD_LINE2+13: LUT_DATA <= 9'h16F;
LCD_LINE2+14: LUT_DATA <= 9'h175;
LCD_LINE2+15: LUT_DATA <= 9'h121;*/
default: LUT_DATA <= 9'dx ;
endcase
end
LCD_Controller u0(
// Host Side
.iDATA(mLCD_DATA),
.iRS(mLCD_RS),
.iStart(mLCD_Start),
.oDone(mLCD_Done),
.iCLK(iCLK),
.iRST_N(iRST_N),
// LCD Interface
.LCD_DATA(LCD_DATA),
.LCD_RW(LCD_RW),
.LCD_EN(LCD_EN),
.LCD_RS(LCD_RS) );
endmodule
Figure 5: Pin assignments for the toggle switches.
Table 2: Pin assignments for LCD coding
Figure 6: Show the coding have no error successful
Figure 7: Show the coding successful
Figure 8: RTL View
OUTPUT
Figure 9 : Output display AINI
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